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US 2018/0025762 A1Published application
Semiconductor device including a column decoder
AssigneeSK hynix Inc.
InventorDuk Su CHUN
Life of this patent
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Abstract
A semiconductor device may be provided. The semiconductor device may include a first power line located in a memory cell array region. The semiconductor device may include a second power line located in a column decoder region. The semiconductor device may include a third power line formed in a layer different from the first power line and the second power line, configured to couple the first power line to the second power line. The semiconductor device may include a metal-oxide-semiconductor (MOS) capacitor located below the third power line.
Claims19
A semiconductor device comprising:
- a first power line located in a memory cell array region, and extended in a first direction;
- a second power line located in a column decoder region, and extended in a second direction crossing the first direction;
- a third power line formed in a layer different from the first power line and the second power line, configured to couple the first power line to the second power line;
- and
- a metal-oxide-semiconductor (MOS) capacitor located below the third power line.
2 more elements
A semiconductor device comprising:
- a plurality of power lines located in a memory cell array region;
- a plurality of signal lines located in the memory cell array region, and arranged between the power lines;
- a plurality of drivers located in a column decoder region, and arranged to correspond to the plurality of signal lines;
- and
- metal-oxide-semiconductor (MOS) capacitors located in the column decoder region, and arranged to correspond to the plurality of power lines.
2 more elements
Dependencies are inferred from the claim text.