US 2018/0025695 A1 · Gate Driver on Array Circuit and Driving Method Thereof, and Display Device

Abstract

The present invention discloses a gate driver on array circuit and a driving method thereof, and a display device. The gate driver on array circuit comprises a first gate driver on array sub-circuit and a second gate driver on array sub-circuit; the first gate driver on array sub-circuit is configured to drive in a first working state which is a state in which no defect occurs in the first gate driver on array sub-circuit; the second gate driver on array sub-circuit is configured to drive in a second working state which is a state in which a defect occurs in the first gate driver on array sub-circuit. The present invention improves the yield rate of the gate driver on array circuit.

Claims14

Dependent claims

A gate driver on array circuit, comprising a first gate driver on array sub-circuit and a second gate driver on array sub-circuit;

the first gate driver on array sub-circuit is configured to drive gate lines in a first working state, wherein the first working state is a state in which no defect occurs in the first gate driver on array sub-circuit;
the second gate driver on array sub-circuit is configured to drive the gate lines in a second working state, wherein the second working state is a state in which a defect occurs in the first gate driver on array sub-circuit.

A driving method for a gate driver on array circuit which comprises a first gate driver on array sub-circuit and a second gate driver on array sub-circuit;

the method comprises:
driving gate lines in a first working state by the first gate driver on array sub-circuit, wherein the first working state is a state in which no defect occurs in the first gate driver on array sub-circuit;
and
driving the gate lines in a second working state by the second gate driver on array sub-circuit, wherein the second working state is a state in which a defect occurs in the first gate driver on array sub-circuit.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

15/656,419Filed 21 Jul 2017

Priority

CN 201610587269.322 Jul 2016

Published

25 Jan 2018

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

G09G 3/3677
Details of drivers for scan electrodes: suitable for active matrices only
G09G 2300/0408
Matrix technologies: integration of the drivers onto the display substrate
G09G 2310/0286
Details of driving circuits: details of a shift registers arranged for use in a driving circuit
G09G 2310/08
Command of the display device: details of timing specific for flat panels, other than clock recovery

Gate Driver on Array Circuit and Driving Method Thereof, and Display Device

Life of this patent

Gate Driver on Array Circuit and Driving Method Thereof, and Display Device

Life of this patent

Abstract

Claims14