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US 2018/0025691 A1Published application
Display control device and display panel module
AssigneeSynaptics Japan GK
InventorsShigeru OTA, Atsushi SHIKATA, Go TOYODA, Makoto TAKEUCHI
Life of this patent
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Abstract
A halt period is inserted between a drive period in an odd-numbered field and a drive period in an even-numbered field in interlace driving. When drive signals driving subpixels are time-divisionally supplied to the display panel in units of subpixel types, switch control signals controlling source line switches which distribute the drive signals associated with respective subpixels to the corresponding source lines are generated so that the number of switching of the source line switches are reduced.
Claims16
A display control device, comprising:
- a gate line controller configured control selection of gate lines of a display panel in synchronization with display timing;
- a source driver configured to supply drive signals to source lines arranged to intersect the gate lines of the display panel;
- and
- a control circuitry configured to control the gate line controller and the source driver,
- wherein the gate line controller separately outputs odd-numbered gate line control signals used for controlling selection of odd-numbered gate lines of the display panel and even-numbered gate line control signals used for controlling selection of even-numbered gate lines,
- wherein the control circuitry is configured to:
- perform, in response to a non-interlace mode being specified, a control to sequentially activate the odd-numbered gate line control signals and the even-numbered gate line control signals in units of gate lines,
- perform, in response to an interlace mode being specified, a control to alternately provide odd field periods and even field periods, and
- perform, in response to an interval interlace mode being specified, a control to provide a gate halt period between every adjacent two of the odd and even field periods provided alternately,
- wherein, in the odd field periods, the odd-numbered gate line control signals are sequentially activated with the even-numbered gate line control signals deactivated,
- wherein, in the even field periods, the even-numbered gate line control signals are sequentially activated with the odd-numbered gate line control signals deactivated, and
- wherein, in the gate halt period, the odd- and even-numbered gate line control signals are both deactivated.
9 more elements
A display panel module, comprising:
- a display panel;
- and
- a display control device including:
- a gate line controller configured to control selection of gate lines of the display panel in synchronization with display timing;
- a source driver configured to supply drive signals in parallel to source lines arranged to intersect the gate lines of the display panel;
- and
- a control circuitry configured to control the gate line controller and the source driver,
- wherein the gate line controller separately outputs odd-numbered gate line control signals used to for controlling selection of odd-numbered gate lines of the display panel and even-numbered gate line control signals used for controlling selection of even-numbered gate lines,
- wherein the control circuitry is configured to perform, in response to a non-interlace mode being specified, a control to sequentially activate the odd-numbered gate line control signals and the even-numbered gate line control signals in units of gate lines, perform, in response to an interlace mode being specified, a control to alternately provide odd field periods and even field periods and perform, in response to an interval interlace mode being specified, a control to provide a gate halt period between adjacent two of the odd and even field periods which are alternately provided,
- wherein, in the odd field periods, the odd-numbered gate line control signals are sequentially activated with the even-numbered gate line control signals deactivated,
- wherein, in the even field periods, the even-numbered gate line control signals are sequentially activated with the odd-numbered gate line control signals deactivated, and
- wherein, in the gate halt period, the odd- and even-numbered gate line control signals are both deactivated.
9 more elements
A display control device, comprising:
- a gate line controller configured control selection of gate lines of a display panel in synchronization with display timing;
- a source driver configured to supply drive signals to source lines arranged to intersect the gate lines of the display panel;
- and
- a control circuitry configured to control the gate line controller and the source driver,
- wherein the gate line controller separately outputs odd-numbered gate line control signals used to for controlling selection of odd-numbered gate lines of the display panel and even-numbered gate line control signals used for controlling selection of even-numbered gate lines,
- wherein the control circuitry is configured to perform, in response to a non-interlace mode being specified, a control to sequentially activate the odd-numbered gate line control signals and the even-numbered gate line control signals in units of gate lines, and perform, in response to an interlace mode being specified, a control to alternately provide odd field periods and even field periods,
- wherein, in the odd field periods, the odd-numbered gate line control signals are sequentially activated and the activation of even-numbered gate line control signals is masked,
- wherein, in the even field periods, the even-numbered gate line control signals are sequentially activated and the activation of the odd-numbered gate line control signals is masked,
- wherein the source driver time-divisionally outputs drive signals to subpixels associated with each gate line from drive terminals in units of subpixel types in each display period associated with each gate line,
- wherein the gate line controller outputs output synchronization signals each specifying an output period in which the drive signals for corresponding one of the subpixel types are to be time-divisionally output from the drive terminals,
- wherein, in response to the interlace or interval interlace mode being specified, the control circuitry performs a control to, in each of the odd field periods, first enable the output synchronization signal which has been last enabled in the display period associated with each of the odd-numbered gate lines in the display period associated with the next odd-numbered gate line, so that the output synchronization signal which has been last enabled in the display period associated with each of the odd-numbered gate lines remain enabled until the display period associated with the next odd-numbered gate line, and a control to, in each of the even field periods, first enable the output synchronization signal which has been last enable in the display period associated with each of the even-numbered gate lines in the display period associated with the next even-numbered gate line, so that the output synchronization signal which has been last enabled in the display period associated with each of the even-numbered gate lines remain enabled until the display period associated with the next even-numbered gate line.
8 more elements
A display panel module, comprising:
- a display panel;
- and
- a display control device including:
- a gate line controller configured to control selection of gate lines of the display panel in synchronization with display timing;
- a source driver configured to supply drive signals in parallel to source lines arranged to intersect the gate lines of the display panel;
- and
- a control circuitry configured to control the gate line controller and the source driver,
- wherein the gate line controller separately outputs odd-numbered gate line control signals used to for controlling selection of odd-numbered gate lines of the display panel and even-numbered gate line control signals used for controlling selection of even-numbered gate lines,
- wherein the control circuitry is configured to perform, in response to a non-interlace mode being specified, a control to sequentially activate the odd-numbered gate line control signals and the even-numbered gate line control signals in units of gate lines, and perform, in response to an interlace mode being specified, a control to alternately provide odd field periods and even field periods,
- wherein, in the odd field periods, the odd-numbered gate line control signals are sequentially activated and the activation of even-numbered gate line control signals is masked,
- wherein, in the even field periods, the even-numbered gate line control signals are sequentially activated and the activation of the odd-numbered gate line control signals is masked,
- wherein the source driver time-divisionally outputs drive signals to subpixels associated with each gate line from drive terminals in units of subpixel types in each display period associated with each gate line,
- wherein the gate line controller outputs output synchronization signals each specifying an output period in which the drive signals for corresponding one of the subpixel types are to be time-divisionally output from the drive terminals,
- wherein the display panel includes a source line switch circuit which distribute the drive signals time-divisionally output from the drive terminals to source lines corresponding to respective subpixels, and
- wherein the source line switch circuit uses the output synchronization signals as switch control signals for the respective subpixel types,
- wherein the control circuitry performs a control to, in each of the odd field periods, first enable the output synchronization signal which has been last enabled in the display period associated with each of the odd-numbered gate lines in the display period associated with the next odd-numbered gate line, so that the output synchronization signal which has been last enabled in the display period associated with each of the odd-numbered gate lines remain enabled until the display period associated with the next odd-numbered gate line, and a control to, in each of the even field periods, first enable the output synchronization signal which has been last enabled in the display period associated with each of the even-numbered gate lines in the display period associated with the next even-numbered gate line, so that the output synchronization signal which has been last enabled in the display period associated with each of the even-numbered gate lines remain enabled until the display period associated with the next even-numbered gate line.
13 more elements
Dependencies are inferred from the claim text.