Method for measuring overlay and measuring apparatus, scanning electron microscope, and gui

A method for measuring overlay at a semiconductor device on which circuit patterns are formed by a plurality of exposure processes, comprising:

• an image capturing step for capturing a plurality of images of areas in the semiconductor device;
• a reference image setting step for setting a reference image on the basis of the plurality of images captured in the image capturing step;
• a difference quantifying step for quantifying a difference between the reference image set in the reference image setting step and the plurality of images captured in the image capturing step;
• and
• an overlay calculating step for calculating the overlay on the basis of the difference quantified in the difference quantifying step.

An apparatus for measuring overlay at a semiconductor device on which circuit patterns are formed by a plurality of exposure processes, comprising:

• an imaging device configured to capture a plurality of images of areas of the semiconductor device;
• an arithmetic unit configured to set a reference image on the basis of the plurality of images, quantify a difference between the reference image and the plurality of images, and calculate the overlay on the basis of the difference;
• and
• a user interface unit configured to control output information on the overlay calculated by the arithmetic unit.

An apparatus for measuring overlay at a semiconductor device on which circuit patterns are formed by a plurality of exposure processes, comprising an imaging device and an arithmetic unit,

• wherein the imaging device is configured to capture a plurality of images of areas of the semiconductor device, and
• wherein the arithmetic unit is configured to:
• recognize, from the plurality of images, each of the circuit patterns formed by each of the plurality of exposure processes;
• separate the circuit patterns into two groups including a first group and a second group, on the basis of an exposure index;
• and
• calculate overlay between circuit patterns of the first groups and circuit patterns of the second groups.