Simulating reference voltage response in digital simulation environments

A method, comprising:

• generating, using one or more computer processors, a digital simulation environment for testing logic representing a physical system;
• delaying a digital signal for testing the logic using a first unequal delay shift to represent a first analog reference voltage, wherein the first unequal delay shift changes a duration of a high cycle in the digital signal relative to a duration of a low cycle in the digital signal;
• receiving updated parameters from the logic in response to providing the digital signal with the first unequal delay shift to the logic;
• and
• delaying, based on the updated parameters, the digital signal using a second unequal delay shift to represent a second analog reference voltage different from the first analog reference voltage.

A computer program product for testing logic representing a physical system, the computer program product comprising:

• a computer-readable storage medium having computer-readable program code embodied therewith, the computer-readable program code executable by one or more computer processors to:
• generate a digital simulation environment for testing the logic;
• delay a digital signal for testing the logic using a first unequal delay shift to represent a first analog reference voltage, wherein the first unequal delay shift changes a duration of a high cycle in the digital signal relative to a duration of a low cycle in the digital signal;
• receive updated parameters from the logic in response to providing the digital signal with the first unequal delay shift to the logic;
• and
• delay, based on the updated parameters, the digital signal using a second unequal delay shift to represent a second analog reference voltage different from the first analog reference voltage.