Staged power on/off sequence at the i/o phy level in an interchip interface

A computer program product for transitioning a bus from a first bandwidth to a second bandwidth, the computer program product comprising a non-transitory computer readable storage medium having program code embodied therewith, the program code readable and executable by a processor to perform a method comprising:

• predicting a bandwidth transition requirement for a bus in a multi-processor computer;
• transitioning the bus from a first bandwidth to a second bandwidth based on the predicted bandwidth transition requirement;
• checking an actual transitioning requirement of the bus in the computer, wherein the bus controller checks the actual transitioning requirement for the bus at each occurrence of a predefined stage of operation of one or more processors in the multi-processor computer;
• and
• directing, in response to the actual transitioning requirement matching the predicted bandwidth transition requirement, a continuation of the transitioning of the bus from the first bandwidth to the second bandwidth.

A computer system comprising one or more processors, one or more computer readable memories, and one or more computer readable storage mediums, and program instructions stored on at least one of the one or more storage mediums for execution by at least one of the one or more processors via at least one of the one or more memories, the stored program instructions comprising:

• program instructions to predict a bandwidth transition requirement for a bus in a multi-processor computer, wherein the bandwidth transition requirement of the bus is predicted based on a workload type for a pending workload in one or more processors in the multi-processor computer;
• program instructions to detect an average cycles/data ratio for the pending workload, wherein the average cycles/data ratio describes an average number of clock cycles required to perform data transfers for the workload type of the pending workload;
• and
• program instructions to transition the bus from a first bandwidth to a second bandwidth based on the average cycles/data ratio for the workload type of the pending workload;
• program instructions to check an actual transitioning requirement of the bus in the processor, wherein the bus controller checks the actual transitioning requirement for the bus at each occurrence of a predefined stage of operation of one or more processors in the multi-processor computer;
• and
• program instructions to, in response to the actual transitioning requirement matching the predicted bandwidth transition requirement, direct a continuation of the transitioning of the bus from the first bandwidth to the second bandwidth.