Techniques to provide a multi-level memory architecture via interconnects

A computer-implemented method, comprising:

• generating compressed data based on a compression mechanism to be applied to data, and
• generating a fabric packet including a compression mechanism indicator, the compressed data, and an address to write the data in at least one of a second level memory and a third level memory, the compression mechanism indicator to indicate which compression mechanism is applied to the data.

An apparatus, comprising:

• a memory interface coupled to a memory controller, the memory interface to:
• receive a fabric packet comprising a compression mechanism indicator, compressed data, and an address to write data in at least one of a second level memory and a third level memory, the compression mechanism indicator to indicate a compression mechanism applied to data to generate the compressed data, and
• decompress the compressed data based on the compression mechansism applied to the compressed data and indicated in the compression mechanism indicator.

A computer-implemented method, comprising;

• receiving a fabric packet comprising a compression mechanism indicator, compressed data, and an address to write data in at least one of a second level memory and a third level memory, the compression mechanism indicator to indicate a compression mechanism applied to data to generate the compressed data, and
• decompressing the compressed data based on the compression mechansism applied to the compressed data and indicated in the compression mechanism indicator.