Ring bus architecture for use in a memory module
AssigneeSanDisk Technologies LLC
InventorAlan Welsh Sinclair
Life of this patent
Estimating the term…
Abstract
Ring bus architectures for use in a memory module are disclosed. A memory module may include a primary ring bus; a ring bus controller positioned on the primary ring bus; a secondary ring bus in communication with the primary ring bus via a first bus bridge; and a tertiary ring bus in communication with the secondary ring bus via a second bus bridge. The ring bus controller is configured to direct the first bus bridge to route data between the primary ring bus and the secondary ring bus and is configured to direct the second bus bridge to route data between the secondary ring bus and the tertiary ring bus.
Claims15
A memory module comprising:
- a primary ring bus;
- a ring bus controller positioned on the primary ring bus;
- a first secondary ring bus in communication with the primary ring bus via a first bus bridge;
- a second secondary ring bus in communication with the primary ring bus via a second bus bridge;
- and
- a tertiary ring bus in communication with the first secondary ring bus via a third ring bus bridge and in communication with the second secondary ring bus via a fourth ring bus bridge;
- wherein the ring bus controller is configured to direct the third bus bridge and the fourth bus bridge to route data between the first secondary ring bus and the second secondary ring bus over the tertiary ring bus without routing data over the primary ring bus.
A memory module comprising:
- a primary ring bus;
- a first secondary ring bus in communication with the primary ring bus via a first bus bridge;
- a second secondary ring bus in communication with the primary ring bus via a second bus bridge;
- and
- a tertiary ring bus in communication with the first secondary ring bus via a third ring bus bridge and in communication with the second secondary ring bus via a fourth ring bus bridge;
- means for directing the third bus bridge and the fourth bus bridge to route data between the first secondary ring bus and the second secondary ring bus over the tertiary ring bus without routing data over the primary ring bus.
A memory module comprising:
- a primary ring bus;
- a first secondary ring bus in communication with the primary ring bus;
- a second secondary ring bus in communication with the primary ring bus:
- a tertiary ring bus in communication with the first secondary ring bus and the second secondary ring bus;
- and
- means for routing data between the first secondary ring bus and the second secondary ring bus over the tertiary ring bus without routing data over the primary ring bus.
Dependencies are inferred from the claim text.