Increasing invalid to modified protocol occurrences in a computing system
AssigneeIntel Corporation
InventorsRaanan Sade, Joseph Nuzman, Stanislav Shwartsman, Igor Yanover, Liron Zur
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AssigneeIntel Corporation
InventorsRaanan Sade, Joseph Nuzman, Stanislav Shwartsman, Igor Yanover, Liron Zur
Estimating the term…
An example system on a chip (SoC) includes a processor, a cache, and a main memory. The SoC can include a first memory to store data in a memory line, wherein the memory line is set to an invalid state. The processor can include a processor coupled to the first memory. The processor can determine that a data size of a first data set received from an application is within a data size range. The processor can determine that an aggregate data size of the first data set and a second data set received from the application is at least a same data size as data size of the memory line. The processor can perform an invalid-to-modify (I2M) operation to change the memory line from the invalid state to a modified state. The processor can write the first data set and the second data set to the memory line.
A multi-core processor comprising:
A system on a chip (SoC), comprising:
A method, comprising:
Dependencies are inferred from the claim text.