Efficient data recovery for write path errors
AssigneeSK hynix Inc.
InventorsYu Cai, Fan Zhang, Sangcheol Lee
Life of this patent
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Abstract
Systems and methods are provided for flash memory devices to improve the write performance in case of write path errors and to hide the write path error correction latency. Some embodiments can provide instant parity correction to allow user data sharing the same strip with the data block having an error to be programmed into the flash memory before the failed data is corrected. Additionally, selected stalling can allow some independent data in different flash memory dies or planes to be programmed during the time of write path error correction.
Claims20
An apparatus comprising:
- a write path error detector configured to detect if a received data block from a set of data blocks has an error;
- a parity calculator configured to calculate a parity data for the data block;
- a processor configured to execute instructions stored in a memory, wherein the instructions stored in the memory cause the processor to perform error correction on the data block with the error;
- and
- a write path manager configured to:
- stall the data block with the error from storing in a flash memory buffer;
- and
- allow storing of subsequent data blocks without error received after the data block with the error into the flash memory buffer during the error correcting of the data block with the error,
- wherein the parity calculator is further configured to recalculate the parity data for the set of data blocks based on the data blocks without error and the error corrected data block.
A method comprising:
- receiving, by a flash memory controller coupled to a flash memory, one data block at a time from a first set of data blocks stored in a volatile memory, wherein the volatile memory stores a plurality of sets of data blocks comprising the first set of data blocks and a second set of data blocks;
- detecting, by the flash memory controller, an error in one of the received data blocks;
- calculating, by the flash memory controller, a parity data based on the received one or more data blocks from the first set of data blocks;
- stalling, by the flash memory controller, the data block with the error from storing in a flash memory buffer;
- error correcting, by the flash memory controller, the data block with the error;
- and
- storing, by the flash memory controller, subsequent data blocks without error received after the data block with the error into the flash memory buffer during the error correcting of the data block with the error.
A non-transitory computer readable medium having stored thereon instructions that, when executed by a processor, perform a method, comprising:
- determining that there is an error in a data block from a set of data blocks, wherein the set of data blocks is stored in a volatile memory communicatively coupled to the processor, wherein the data block with the error is stalled from storing in a flash memory buffer coupled to the processor;
- error correcting the data block with the error;
- and
- storing subsequent data blocks without error received after the data block with the error into the flash memory buffer during the error correcting of the data block with the error.
Dependencies are inferred from the claim text.