Optimize data protection layouts based on distributed flash wear leveling

A tangible, non-transitory, computer-readable media having instructions thereupon which, when executed by a processor, cause the processor to perform a method comprising:

• identifying a first portion of solid-state memory of a storage system that has a lower read latency than a second portion of the solid-state memory;
• writing a first portion of each of a plurality of error correction coded words to the first portion of the solid-state memory;
• and
• writing a second portion of each of the plurality of error correction coded words to the second portion of the solid-state memory.

A storage system, comprising:

• solid-state memory;
• and
• one or more processors, configurable to:
• identify a first portion of the solid-state memory that has a lower read latency than a second portion of the solid-state memory;
• write a first portion of each of a plurality of error correction coded words to the first portion of the solid-state memory;
• and
• write a second portion of each of the plurality of error correction coded words to the second portion of the solid-state memory.