Pc-relative addressing and transmission

A system, comprising:

• a processor;
• and
• a memory storing a program, which, when executed on the processor, performs an operation for processing instructions, the operation comprising:
• receiving a plurality of instructions from a program counter (PC) operable to be fused into a PC-relative plus offset instruction;
• fusing the plurality of instructions into an internal operation (IOP) that specifies PC-relative addressing with an offset;
• computing a shared PC portion comprising one or more common upper bits of a PC address of each of the plurality of instructions;
• if the shared PC portion is different than a previously computed shared PC portion, transmitting the shared PC portion to one or more downstream components in the processor pipeline;
• transmitting the IOP with a representation of lower order bits of the PC address;
• and
• processing the IOP.

A computer program product for processing instructions, the computer program product comprising a non-transitory computer-readable storage medium having computer-readable program code embodied therewith, the computer-readable program code executable by a processor to cause the processor to:

• receive a plurality of instructions from a program counter (PC) operable to be fused into a PC-relative plus offset instruction;
• fuse the plurality of instructions into an internal operation (IOP) that specifies PC-relative addressing with an offset;
• compute a shared PC portion comprising one or more common upper bits of a PC address of each of the plurality of instructions;
• if the shared PC portion is different than a previously computed shared PC portion, transmit the shared PC portion to one or more downstream components in the processor pipeline;
• transmit the IOP with a representation of lower order bits of the PC address;
• and
• process the IOP.