Processor testing
AssigneeInternational Business Machines Corporation
InventorsAbhishek Bansal, Nitin P. Gupta, Brad L. Herold, Jayakumar N. Sankarannair
Life of this patent
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AssigneeInternational Business Machines Corporation
InventorsAbhishek Bansal, Nitin P. Gupta, Brad L. Herold, Jayakumar N. Sankarannair
Estimating the term…
A process for processor testing includes generating a set of test instructions having a first portion and a second portion. A first branch instruction is randomly generated for the first portion where the first branch instruction branches to a respective instruction in a second portion by a branching location offset. A second branch instruction is randomly generated for the second portion where the second branch instruction branches to a respective instruction in the first portion by the branching location offset. If additional instructions are to be added to the set of test instructions, a value of the branching location offset is incrementing by a predetermined amount.
A method comprising:
A system comprising:
A computer program product for generating test instructions for a processor, the computer program product comprising:
Dependencies are inferred from the claim text.