Configuration and testing method and system for fpga chip using bumping process

A method of configuration and test of an FPGA chip, comprising the steps of:

• 1) creating configuration files for an FPGA chip under test and storing the configuration files in a mass memory, the configuration files comprising information about a plurality of configuration resources required for function test of the FPGA chip under test, wherein each of a plurality of configuration codes comprised in the configuration files is mapped to a corresponding one of the plurality of configuration resources;
• 2) reading, by a master FPGA, a configuration code stream comprising corresponding configuration codes from the mass memory according to a control test algorithm developed based on an automatic test equipment (ATE), configuring the FPGA chip under test via an external test interface, and determining whether the configuration is successful;
• 3) if the configuration is successful, converting the successfully configured configuration code stream into a test signal source file recognizable and executable by the ATE by using the control test algorithm and a conversion tool, the test signal source file comprising test signal source codes reusable by multiple test equipment;
• and
• 4) automatically loading the test signal source file onto the FPGA chip under test by the ATE in real time, collecting responses output from the FPGA chip under test, determining and analyzing test results and outputting a test data log, thereby completing the function test and corresponding performance test.

A configuration and test system for an FPGA chip, comprising:

• an automatic test equipment (ATE) test module, which provides a request signal for configuration of an FPGA chip under test, generates a test signal, applies a test signal source file onto the FPGA chip under test and determines and analyzes test results output therefrom, thereby accomplishing test of the FPGA chip under test;
• a test and configuration board controlled by the ATE test module, the test and configuration board comprising a master FPGA and a mass memory;
• and
• a computer, adapted to configure the master FPGA of the test and configuration board, create configuration files and download configuration data for the FPGA chip under test;
• wherein the mass memory is adapted to store the created configuration files, wherein with a control test algorithm configured on the ATE, the master FPGA reads a configuration code stream from the mass memory, configures the FPGA chip under test via an external interface, determines whether the configuration is successful, wherein if the configuration is successful, the successfully configured configuration code stream is converted into a test signal source file recognizable and executable by the ATE by using the control test algorithm and a conversion tool, and wherein the test signal source file comprises test signal source codes reusable by multiple test equipments.