Test pattern count reduction for testing delay faults

A system comprising:

• a testing arrangement to receive a Device Under Test (DUT), and to test the DUT;
• and
• a computing environment coupled to the testing arrangement, the computing environment comprising:
• a memory to store instructions;
• and
• a processor coupled to the memory, the processor to:
• identify a plurality of transition faults that is to possibly occur in the DUT;
• generate a set comprising a plurality of modified fault expressions, at least one of the plurality of modified fault expressions being associated with a corresponding transition fault of the plurality of transition faults;
• identify, during a first iteration, a first test pattern that is to satisfy a first number of modified fault expressions of the set, and
• update the set, by removing the first number of modified fault expressions from the set, to generate a first updated set.

A method comprising:

• identifying a plurality of transition faults that can possibly occur in a circuit;
• generating a plurality of fault expressions respectively corresponding to the plurality of transition faults;
• selecting a first subset of the fault expressions from the plurality of fault expressions, such that for at least one fault expression in the first subset, there exists at least one corresponding output of the circuit that is at an incorrect state for more than a threshold period of time, if the corresponding transition fault is to occur;
• and
• generating a plurality of test patterns for testing the circuit, based at least in part on the first subset of fault expressions.

An apparatus comprising:

• a memory to store instructions;
• and
• a processor coupled to the memory, the processor to perform operations comprising:
• identify a plurality of transition faults that can possibly occur in a Device Under Test (DUT);
• generate a plurality of fault expressions respectively corresponding to the plurality of transition faults;
• select a first subset of the fault expressions from the plurality of fault expressions, such that for at least one fault expression in the first subset, there exists at least one corresponding output of the DUT that is at an incorrect state for more than a threshold period of time, if the corresponding transition fault is to occur;
• generate a plurality of test patterns for testing the DUT, based at least in part on the first subset of fault expressions;
• and
• transmit the plurality of test patterns to a tester for testing the DUT