High speed double data rate jtag interface
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel
Life of this patent
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Abstract
A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface (202). The access is accomplished by combining the separate TDI and TMS signals from the TAP controller into a single signal and communicating the TDI and TMS signals of the single signal on the rising and falling edges of the TCK driving the DDR interface. The TAP domain may be coupled to the TAP controller in a point to point fashion or in an addressable bus fashion. The access to the TAP domain may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.
Claims4
An integrated circuit comprising:
- (a) a TDI/TMS signal and a TCK signal;
- (b) double data rate circuitry having a TDI/TMS input coupled to the TDI/TMS signal, a TCK input coupled to the TCK signal, a DDR TDI output, and a DDR TMS output;
- (c) a TAP domain having a domain TDI input, a domain TMS input, and a domain TCK input;
- and
- (d) addressable TAP interface circuitry having a TDI input coupled to the DDR TDI output, a TMS input coupled to the DDR TMS output, a TCK input coupled to the TCK signal, a domain TDI output coupled to the domain TDI input, a domain TMS output coupled to the domain TMS input, and a domain TCK output coupled to the domain TCK input, the addressable TAP interface including:
- i. a state machine having a Test Data In input coupled to the TDI input, a Clock input coupled to the TCK input, a Match input, an Address In output, an Address Control output, an enable input, and a reset input;
- and
- ii. a TAP state monitor having a Test Mode Select input coupled to the TMS input, a Clock input coupled to the TCK input, an enable output coupled to the enable input, and a reset output coupled to the reset input.
Dependencies are inferred from the claim text.