Fault current limiter

A fault current limiter apparatus comprising:

• a fault current limiter including:
• a magnetically saturable core, at least one AC coil wound on at least a portion of the magnetically saturable core, and a magnetic biasing arrangement for magnetically biasing at least a portion of the magnetically saturable core;
• a source terminal for electrically connecting the fault current limiter to a power source, and a load terminal for electrically connecting the fault current limiter to a load, wherein the at least one AC coil of the fault current limiter is electrically connected between the source and load terminals, and wherein the fault current limiter has a first inductance in normal conditions and a second inductance in fault conditions;
• a first capacitance electrically connected between the source and load terminals, wherein the first capacitance is electrically connected in series with the fault current limiter, and wherein the first capacitance has a capacitance that is arranged to have a reactance value that compensates for at least some of the first inductance.

A fault current limiter apparatus comprising:

• a fault current limiter including:
• a magnetically saturable core, at least one AC coil wound on at least a portion of the magnetically saturable core, and a magnetic biasing arrangement for magnetically biasing the at least a portion of the magnetically saturable core;
• a source terminal for electrically connecting the fault current limiter to a power source, and a load terminal for electrically connecting the fault current limiter to a load, wherein the at least one AC coil of the fault current limiter is electrically connected between the source and load terminals, and wherein the fault current limiter has a first inductance in normal conditions and a second inductance in fault conditions;
• a first capacitance electrically connected between the source and load terminals, wherein the first capacitance is electrically connected in parallel with the fault current limiter, and wherein the first capacitance has a reactance that is arranged to correspond to the second inductance.