Multi-level air gap formation in dual-damascene structure
AssigneeInternational Business Machines Corporation
InventorsRichard A. Conti, Jessica Dechene, Susan S. Fan, Son V. Nguyen, Jeffrey C. Shearer
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Abstract
An upper layer is formed in a first interlayer dielectric (ILD) layer. The upper layer comprises a plurality of metal interconnects and one or more upper layer air gaps positioned between adjacent metal interconnects. A lower layer is formed in the first ILD layer. The lower layer comprises one or more vias, and one or more lower air gaps positioned between adjacent vias. The upper layer and the lower layer are formed in accordance with a dual-damascene process.
Claims20
A semiconductor structure formed in accordance with a dual-damascene process comprising:
- an upper layer formed in a first interlayer dielectric (ILD) layer, the upper layer comprising:
- a plurality of metal interconnects;
- and
- one or more upper layer air gaps positioned between adjacent metal interconnects;
- and
- a lower layer formed in the first ILD layer, the lower layer comprising:
- one or more vias;
- and
- one or more lower layer air gaps positioned between adjacent vias.
An integrated circuit comprising:
- an upper layer formed in a first interlayer dielectric (ILD) layer, the upper layer comprising:
- a plurality of metal interconnects;
- and
- one or more upper layer air gaps positioned between adjacent metal interconnects;
- and
- a lower layer formed in the first ILD layer, the lower layer comprising:
- one or more vias;
- and
- one or more lower layer air gaps positioned between adjacent vias;
- wherein the upper layer and the lower layer are formed in accordance with a dual-damascene process.
Dependencies are inferred from the claim text.