Delta sigma modulator with excess loop delay compensation

A delta sigma modulator circuit, comprising:

• a signal processor circuit configured to receive an input signal and a feedback signal and generate a processed signal using the input signal and the feedback signal;
• a quantizer configured to generate a digital code using the processed signal;
• a rotating splitter configured to receive the digital code and segment the digital code to form a segmented digital code that is smaller in size than the digital code;
• a rotation circuit configured to receive the segmented digital code and rotate the segmented digital code to generate a rotated digital code;
• and
• an digital-to-analog converter (DAC) configured to receive the rotated digital code and generate the feedback signal using the rotated digital code.

A method of performing delta sigma modulation, comprising:

• receiving an input signal;
• generating a processed signal using the input signal and a feedback signal;
• digitizing the processed signal to generate a digital code;
• segmenting the digital code to form a segmented digital code that is smaller in size than the digital code;
• rotating the segmented digital code to compensate for an excess loop delay and form a rotated digital code;
• and
• generating the feedback signal at least in part by converting the rotated digital code into an analog signal.