High speed voltage level shifter

A method for level shifting an input signal from a first power domain to a second power domain using a voltage level shifter, the voltage level shifter comprising first and second p-type metal-oxide-semiconductor (PMOS) transistors coupled in series between a supply voltage of the second power domain and a node, and a first n-type metal-oxide-semiconductor (NMOS) transistor coupled between the node and a ground, the method comprising;

• inputting the input signal in the first power domain to a gate of the first PMOS transistor and a gate of the first NMOS transistor;
• inverting a signal at the node to obtain an inverted signal;
• and
• inputting the inverted signal to a gate of the second PMOS transistor.

An interface, comprising:

• a first buffer in a first power domain;
• and
• voltage level shifter, comprising:
• a first p-type metal-oxide-semiconductor (PMOS) transistor having a gate configured to receive an input signal from the first buffer;
• a second PMOS transistor, wherein the first and second PMOS transistors are coupled in series between a supply voltage of a second power domain and a node;
• an inverter having an input coupled to the node and an output coupled to a gate of the second PMOS transistor;
• and
• a first n-type metal-oxide-semiconductor (NMOS) transistor having a gate configured to receive the input signal from the first buffer, wherein the first NMOS transistor is coupled between the node and a ground.