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US 2018/0006132 A1Published application
Varied silicon richness silicon nitride formation
AssigneeCypress Semiconductor Corporation
InventorsYi Ma, Shenqing Fang, Robert Ogle
Life of this patent
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Abstract
A method to fabricate a non-planar memory device including forming a multi-layer silicon nitride structure substantially perpendicular to a top surface of the substrate. There may be multiple non-stoichiometric silicon nitride layers, each including a different or same silicon richness value from one another.
Claims21
A method of fabricating a three-dimensional (3D) device, comprising:
- forming a stack, including multiple sacrificial nitride and inter-cell dielectric layers arranged in an alternating arrangement, overlying a substrate;
- etching at least one opening that is substantially vertical, in the stack;
- forming a blocking dielectric layer overlying an inner surface of the at least one opening;
- depositing, using a first atomic layer deposition (ALD) process, a first silicon nitride layer having a first silicon richness value abutting the blocking dielectric layer;
- pre-determining an initial silicon richness value;
- depositing, using a second ALD process, a second silicon nitride layer having the initial silicon richness value, abutting the first silicon nitride layer;
- adjusting the initial silicon richness value to a first updated silicon richness value;
- and
- depositing, using a third ALD process, a third silicon nitride layer having the first updated silicon richness value.
6 more elements
A method of fabricating a non-planar memory device, comprising:
- forming a stack including alternating sacrificial nitride and inter-cell dielectric layers;
- forming a device opening that is substantially vertical and depositing a blocking dielectric layer onto an inner wall of the device opening;
- and
- forming a multi-layer silicon nitride structure abutting the blocking dielectric layer, wherein the multi-layer silicon nitride structure includes,
- a first stoichiometric silicon nitride layer abutting the blocking dielectric layer, and
- N layers of non-stoichiometric silicon nitride layers disposed sequentially overlying the first stoichiometric silicon nitride layer, wherein N is a natural number greater than 1, a first layer of the N layers abutting the first stoichiometric silicon nitride layer and an Nth layer abutting an (N−1)th layer, wherein each of the N layers of non-stoichiometric silicon nitride layers has a silicon richness value that is mutually different from one another.
3 more elements
A method of fabricating a memory device, comprising:
- forming a stack including alternating sacrificial nitride and inter-cell dielectric layers;
- forming a device opening that is substantially vertical and depositing a blocking dielectric layer onto an inner wall of the device opening;
- depositing via a first atomic layer deposition a first stoichiometric silicon nitride layer onto the blocking dielectric layer;
- depositing via a second atomic layer deposition a first non-stoichiometric silicon nitride layer onto the first stoichiometric silicon nitride layer, the first non-stoichiometric silicon nitride layer having a first silicon richness value;
- increasing the first silicon richness value by a predefined amount to produce a second silicon richness value;
- depositing via a third atomic layer deposition a second non-stoichiometric silicon nitride layer onto the first non-stoichiometric silicon nitride layer, the second silicon nitride layer having the second silicon richness value;
- increasing the second silicon richness value by another predefined amount to produce a third silicon richness value;
- and
- depositing via a fourth atomic layer deposition a third non-stoichiometric silicon nitride layer onto the second non-stoichiometric silicon nitride layer, the third non-stoichiometric silicon nitride layer having the third silicon richness value.
6 more elements
Dependencies are inferred from the claim text.