Subtractive vfet process flow with replacement metal gate and metallic source/drain

A method of forming a vertical FET (Field Effect Transistor) structure, comprising:

• forming a fin;
• depositing a first dielectric around said fin;
• forming a first encapsulating region along a top portion of said fin;
• removing said first dielectric from the unencapsulated portion of said fin;
• forming a bottom source-drain region along a bottom portion of said fin;
• removing said first encapsulating region;
• forming a bottom sidewall spacer region above the bottom source/drain region;
• forming a dummy gate region above the bottom sidewall spacer region;
• forming a second encapsulating region around the remaining top portion of the fin above the dummy gate region;
• removing said dummy gate region to form a replacement gate cavity;
• removing said first dielectric in the replacement gate cavity;
• etching a portion of the fin region exposed by the removal of said first dielectric in said replacement gate cavity;
• filling the replacement gate cavity with a replacement gate stack;
• recessing the replacement gate stack to a height below the top surface of said fin;
• forming a top sidewall spacer region;
• and
• forming a top source-drain region.