Three dimensional semiconductor memory device

A three-dimensional semiconductor memory device, comprising:

• a first selection structure extending along a first direction and including a plurality of first selection conductive patterns vertically stacked on a substrate;
• a second selection structure adjacent to the first selection structure and including a plurality of second selection conductive patterns vertically stacked on the substrate;
• first and second channel structures penetrating the first and second selection structures, respectively;
• an upper interconnection line crossing the first and second selection structures;
• and
• first and second conductive pads provided on the first and second channel structures, respectively, to electrically connect the upper interconnection line to the first and second channel structures,
• wherein bottom surfaces of the first and second conductive pads are positioned below top surfaces of the uppermost first and second selection conductive patterns,
• wherein the first conductive pad includes impurities of a first conductivity type, and the first channel structure comprises a channel impurity region having impurities of a second conductivity type and positioned adjacent to the first selection conductive patterns,
• wherein the bottom surface of the first conductive pad is separated from the channel impurity region.

A three-dimensional semiconductor memory device, comprising:

• a substrate;
• a vertical channel formed on the substrate;
• a conductive pad formed on the vertical channel, wherein the conductive pad includes impurities of a first conductivity type;
• a bit line formed on the conductive pad, wherein the bit line is electrically coupled to the conductive pad;
• a plurality of word lines vertically formed on the substrate which is adjacent to the vertical channel;
• and
• a plurality of selection conductive patterns vertically formed on the plurality of word lines,
• wherein the vertical channel includes a channel impurity region and an offset region, wherein the offset region is interposed between the conductive pad and the channel impurity region, and wherein the channel impurity region has impurities of a second conductivity type.