Decision feedback equalizer and semiconductor integrated circuit

A semiconductor integrated circuit comprising:

• a decision feedback equalizer configured to decide data being sampled from an input serial signals on the basis of a clock signal;
• a multiplexer configured to output a parallel signal in accordance with an output signal of the decision feedback equalizer;
• and
• a clock recovery circuit configured to control a phase of the clock signal on the basis of a received signal, wherein the decision feedback equalizer includes:
• a comparator configured to a constant voltage in a reset period and to output a differential voltage corresponding to differential input signals in an evaluation period,
• a latch circuit configured to hold the differential voltage in the evaluation period, and
• an adjuster configured to adjust a logical threshold of the latch circuit closer to the output voltage in the reset period.