Standard cell architecture for reduced parasitic resistance and improved datapath speed

A method of operating a metal oxide semiconductor (MOS) device, the method comprising:

• propagating a first signal through a first logic component with a first input and a first output, the first input being located on a first track extending in a first direction and a second track extending in a second direction orthogonal to the first direction, the first output being located on the first track and a third track extending in the second direction;
• propagating a second signal through a second logic component with a second input and a second output, the second input being located on the first track and a fourth track extending in the second direction, the second output being located on the first track and a fifth track extending in the second direction, the fourth track and the fifth track being between the second track and the third track, wherein the MOS IC device comprises:
• a first interconnect on a metal x (Mx) layer extending on the first track and coupled to the first input on the second track;
• a second interconnect on the Mx layer extending on the first track and coupled to the first output on the third track;
• a third interconnect on a metal y (My) layer extending on the first track and coupled to the second input on the fourth track, y being greater than x;
• and
• a fourth interconnect on the My layer extending on the first track and coupled to the second output on the fifth track.

A metal oxide semiconductor (MOS) device, comprising:

• first means for propagating a first signal through a first logic component with a first input and a first output, the first input being located on a first track extending in a first direction and a second track extending in a second direction orthogonal to the first direction, the first output being located on the first track and a third track extending in the second direction;
• and
• second means for propagating a second signal through a second logic component with a second input and a second output, the second input being located on the first track and a fourth track extending in the second direction, the second output being located on the first track and a fifth track extending in the second direction, the fourth track and the fifth track being between the second track and the third track, wherein the MOS IC device further comprises:
• a first interconnect on a metal x (Mx) layer extending on the first track and coupled to the first input on the second track;
• a second interconnect on the Mx layer extending on the first track and coupled to the first output on the third track;
• a third interconnect on a metal y (My) layer extending on the first track and coupled to the second input on the fourth track, y being greater than x;
• and
• a fourth interconnect on the My layer extending on the first track and coupled to the second output on the fifth track.