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US 2017/0373587 A1Published application
Compact partitioned capacitor for multiple voltage domains with improved decoupling
AssigneeIntel Corporation
InventorsChin Lee Kuan, Sameer Shekhar, Amit K. Jain
Life of this patent
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Abstract
Methods and apparatus relating to a compact partitioned capacitor design for multiple voltage and/or load domains (e.g., with improved decoupling) are described. In an embodiment, a capacitor provides substrate decoupling for a plurality of loads. Moreover, the capacitor is capable of decoupling two or more voltage domains. Furthermore, in some embodiments the capacitor is capable of decoupling two or more voltage domains and mitigating self-noise and/or cross-noise between them. Other embodiments are also disclosed and claimed.
Claims25
An apparatus comprising:
- a capacitor coupled to voltage regulator logic,
- wherein the capacitor is to provide substrate decoupling for a plurality of loads and wherein the capacitor is to decouple two or more voltage domains.
A computing system comprising:
- memory to store data;
- a processor, coupled to the memory, to perform one or more operations on the stored data;
- and
- a capacitor coupled to voltage regulator logic,
- wherein the capacitor is to provide substrate decoupling for a plurality of loads and wherein the capacitor is to decouple two or more voltage domains.
2 more elements
Dependencies are inferred from the claim text.