Single or mutli block mask management for spacer height and defect reduction for beol

A method of making a semiconductor structure comprising:

• providing a first semiconductor block stack comprising a first plurality of spacers on top of a first TiN layer, a first organic planarization layer on top of the first plurality of spacers, and a first SiARC layer on top of the organic planarization layer;
• forming a first inverted mask on the first semiconductor block stack, the first inverted mask comprising a first inverted mask opening,
• eroding the portion of the plurality of spacers below the first inverted mask opening;
• depositing a first fill material masking the portion of the first plurality of spacers below the first inverted mask opening;
• providing a second semiconductor block stack comprising a second plurality of spacers on top of a second TiN layer and a second organic planarization layer on top of the second plurality of spacers,
• depositing a second SiARC layer on top of the semiconductor structure;
• forming a second inverted mask on the semiconductor structure, the second inverted mask including a second inverted mask opening,
• eroding the portion of the plurality of spacers below the second inverted mask opening;
• and
• depositing a second fill material masking the portion of the second plurality of spacers below the second inverted mask opening.

A method of making a semiconductor structure comprising:

• providing a semiconductor structure comprising a plurality of spacers on a bottom TiN layer,
• depositing on the plurality of spacers:
• a bottom organic planarization layer,
• a top TiN layer,
• an LTO mask,
• a top organic planarization layer, and
• a top SiARC layer;
• patterning a first mask on the semiconductor structure, the first mask defining a first unmasked region;
• opening the semiconductor structure to the top TiN layer in the first unmasked region and removing the top SiARC layer;
• replacing the top organic planarization layer with a second top organic planarization layer;
• depositing a second top SiARC layer on the semiconductor structure;
• patterning a second mask on the semiconductor structure, the first mask and second mask defining a second unmasked region;
• etching the bottom TiN layer in the second unmasked region.