Ots for nvm array select lines

A memory device, comprising:

• a word line;
• a bit line disposed perpendicular to the word line;
• a memory element disposed between the word line and the bit line;
• a select element coupled to the memory element, wherein the select element is disposed adjacent to the word line;
• a wire that at least partly overlaps the bit line, the wire coupled with a voltage source providing a predefined unselect bias voltage;
• and
• a connecting element disposed between the bit line and the wire wherein the connecting element comprises a second memory element and a second select element wherein the second select element is constructed from one of a RRAM and a MRAM material.

A memory array, comprising:

• a plurality of word lines;
• a plurality of bit lines that are disposed perpendicular to the plurality of word lines;
• a plurality of memory devices, each memory device of the plurality of memory devices disposed between a respective word line of the plurality of word lines and a respective bit line of the plurality of bit lines, each memory device respectively comprising:
• a memory element;
• and
• a select element coupled to the memory element, wherein the select element is disposed adjacent to the respective word line or to the respective bit line;
• a wire that at least partly overlaps (i) each of the plurality of word lines or (ii) each of the plurality of bit lines, the wire coupled with a voltage source providing a predefined unselect bias voltage;
• and
• a plurality of connecting elements, each connecting element of the plurality of connecting elements disposed between (i) the wire and a respective word line of the plurality of word lines or (ii) the wire and a respective bit line of the plurality of bit lines wherein each connecting element of the plurality of connecting elements respectively comprises a second memory element and a second select element wherein the second select element is constructed from one of a RRAM and a MRAM material.