Memory controller that forces prefetches in response to a present row address change timing constraint

A computing system, comprising:

• one or more processing cores;
• a system memory;
• a networking interface;
• a memory controller coupled to the system memory, the memory controller comprising a), b) and c) below:
• a) prefetch circuitry to prefetch, from a memory, data having a same row address in response to the memory controller's servicing of its request stream being stalled because of a timing constraint that prevents a change in row address;
• b) a cache to cache the prefetched data;
• c) circuitry to compare addresses of read requests in the memory controller's request stream against respective addresses of the prefetched data in the cache and to service those of the requests in the memory controller's request stream having a matching address with corresponding ones of the prefetched data in the cache

A method, comprising:

• recognizing that a next request in a memory controller request stream cannot be issued to a memory because the next request would include a row address change and a timing constraint of the memory presently does not permit the row address change;
• in response to the recognizing, prefetching a plurality of data items from the memory without changing the row address;
• caching the pre-fetched data items;
• and,
• servicing certain read requests of the memory controller request stream with respective ones of the pre-fetched data items where a prefetched data item used to service a read request has an address that matches the read request.