Iteration Synchronization Construct for Parallel Pipelines

A processing device for managing operations in a parallel pipeline, the processing device configured to perform operations comprising:

• initializing a plurality of instances of an iteration synchronization construct (ISC) for a plurality of stage iterations of a parallel stage of the parallel pipeline, wherein the plurality of instances of the ISC includes a first instance of the ISC for a first stage iteration of a first parallel stage of the parallel pipeline and a second instance of the ISC for a second stage iteration of the first parallel stage of the parallel pipeline;
• determining whether execution of the first stage iteration is complete;
• and
• sending a ready signal from the first instance of the ISC to the second instance of the ISC in response to determining that execution of the first stage iteration is complete.

A processing device for managing operations in a parallel pipeline, comprising:

• means for initializing a plurality of instances of an iteration synchronization construct (ISC) for a plurality of stage iterations of a parallel stage of the parallel pipeline, wherein the plurality of instances of the ISC includes a first instance of the ISC for a first stage iteration of a first parallel stage of the parallel pipeline and a second instance of the ISC for a second stage iteration of the first parallel stage of the parallel pipeline;
• means for determining whether execution of the first stage iteration is complete;
• and
• means for sending a ready signal from the first instance of the ISC to the second instance of the ISC in response to determining that execution of the first stage iteration is complete.

A non-transitory processor-readable storage medium having stored thereon processor-executable instructions configured to cause a processor of a computing device to perform operations comprising:

• initializing a plurality of instances of an iteration synchronization construct (ISC) for a plurality of stage iterations of a parallel stage of a parallel pipeline, wherein the plurality of instances of the ISC includes a first instance of the ISC for a first stage iteration of a first parallel stage of the parallel pipeline and a second instance of the ISC for a second stage iteration of the first parallel stage of the parallel pipeline;
• determining whether execution of the first stage iteration is complete;
• and
• sending a ready signal from the first instance of the ISC to the second instance of the ISC in response to determining that execution of the first stage iteration is complete.