Processor with slave free list that handles overflow of recycled physical registers and method of recycling physical registers in a processor using a slave free list

A processor, comprising:

• a plurality of physical registers, each identified by a physical register index;
• a reorder buffer comprising a plurality of instruction entries each storing up to two physical register indexes for recycling corresponding physical registers, wherein each of said plurality of instruction entries corresponds with an instruction that is retired by said reorder buffer;
• a master queue and a slave queue, each comprising a plurality of input ports;
• a master recycle circuit that routes a first physical register index, which is stored in an instruction entry of an instruction, to said master queue when said instruction is retired;
• a slave recycle circuit that routes a second physical register index, which is stored in said instruction entry of said instruction, to said slave queue when said instruction is retired;
• and
• a transfer controller that transfers at least one physical register index stored in said slave queue to said master queue in a processor cycle when said master queue has at least one available input port.

A method of recycling physical registers in a processor, comprising:

• retiring, by a reorder buffer, up to N instructions in each processor cycle;
• for each instruction being retired:
• when a first physical register is identified to be recycled upon retirement of the instruction, routing a corresponding first physical register index to a master free list;
• and
• when a second physical register is identified to be recycled upon retirement of the instruction, routing a corresponding second physical register index to a slave free list;
• and
• allocating physical registers whose corresponding physical register indexes are stored in the master free list to instructions being issued.