Information processing system

An information processing system comprising:

• a first processor;
• a second processor coupled to the first processor;
• a first buffer circuit coupled to the second processor;
• and
• a first memory coupled to the second processor, wherein
• the first processor is configured to generate a first read command specifying a first data stored in a first address area of the first memory,
• the second processor is configured to generate, based on the first read command, a second read command specifying a second data stored in a second address area of the first memory different from the first address area,
• the second processor is configured to control, based on a number of the first read command stored in the first buffer circuit, a timing of transmitting the generated second read command to the first buffer circuit,
• the first buffer circuit is configured to store the first read command and the second read command, and
• the second processor is configured to execute the first read command and the second read command stored in the first buffer circuit.

An information processing system comprising:

• a first processor;
• a second processor coupled to the first processor;
• a first memory coupled to the second processor;
• and
• a second memory coupled to the first processor, wherein
• the first processor is configured to generate a first read command specifying a first data stored in a first address area of the first memory,
• the second processor is configured to generate, based on the first read command, a second read command specifying a second data stored in a second address area of the first memory different from the first address area,
• the second processor is configured to read the first data and the second data from the first memory by executing the first read command and the second read command,
• the second memory is configured to store the first data and the second data read from the first memory, and
• the second processor is configured not to generate a third read command specifying the second address area when a fourth read command specifying the second address area is not generated by the first processor within a certain period of time after the second data is stored in the second memory and when a fifth read command specifying the first address area is generated by the first processor after the certain period of time has elapsed.