Method and apparatus for memory efficiency improvement by providing burst memory access control
AssigneeAdvanced Micro Devices, Inc.
InventorsShuzhi Hou, Sadagopan Srinivasan, Daniel L. Bouvier
Life of this patent
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Abstract
Methods and apparatus monitor memory access activities of non-real-time processing engines to determine time intervals when the memory access activities are low. When such time intervals are found, the methods and apparatus perform burst memory access control for real-time processing engines by bursting data from a memory to a burst memory buffer, or from the burst memory buffer to the memory, to allow fast data access by the real-time processing engines.
Claims20
A method for controlling memory access to a memory by a memory controller, the method comprising:
- determining, by the memory controller, a plurality of low memory access activity durations during a display frame processing interval associated with a first processing engine;
- and
- controlling, by the memory controller, the memory for a second processing engine during the plurality of low memory access activity durations determined in the display frame processing interval to burst data for a burst memory buffer.
An apparatus comprising:
- a memory controller;
- a memory operatively coupled to the memory controller;
- a burst memory buffer operatively coupled to the memory controller;
- a first processing engine operatively coupled to the memory controller;
- and
- a second processing engine operatively coupled to the memory controller;
- the memory controller configured to:
- determine a plurality of low memory access activity durations during a display frame processing interval associated with the first processing engine;
- and
- control the memory for the second processing engine during the plurality of low memory access activity durations determined in the display frame processing interval to burst data for the burst memory buffer.
An apparatus comprising:
- a memory controller;
- a memory operatively coupled to the memory controller;
- an input and output (I/O) controller operatively coupled to the memory controller;
- a burst memory buffer operatively coupled to the memory controller and to the I/O controller;
- a first processing engine operatively coupled to the memory controller;
- and
- a second processing engine operatively coupled to the I/O controller;
- the memory controller configured to:
- determine a plurality of low memory access activity durations during a display frame processing interval associated with the first processing engine;
- and
- control the memory for the second processing engine during the plurality of low memory access activity durations determined in the display frame processing interval to burst data for the burst memory buffer.
Dependencies are inferred from the claim text.