Damage Implantation of a Cap Layer
AssigneeTexas Instruments Incorporated
InventorsMahalingam Nandakumar, Wayne Bather, Narendra Singh Mehta
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Abstract
A method for fabricating a transistor on a semiconductor wafer includes providing a partial transistor containing a gate stack, extension regions, and source/drain sidewalls, The method also includes performing a source/drain implant of the semiconductor wafer, forming a cap layer over the semiconductor wafer, and performing a source/drain anneal. In addition, the method includes performing a damage implant of the cap layer and removing the cap layer over the semiconductor wafer.
Claims12
An integrated circuit comprising:
- a silicon oxide liner film in contact with annealed source/drain regions and a gate electrode of a transistor;
- and
- a cap layer comprising silicon and nitrogen in contact with said silicon oxide liner film;
- wherein said cap layer contains an electrically neutral species.
An integrated circuit comprising:
- a silicon oxide liner film in contact with annealed source/drain regions and a gate electrode of a transistor;
- and
- a cap layer comprising silicon and carbon in contact with said silicon oxide liner film;
- wherein said cap layer contains an electrically neutral species.
An integrated circuit comprising:
- a cap layer comprising silicon and nitrogen in contact with unannealed source/drain regions and a gate electrode of a transistor;
- wherein said cap layer contains an electrically neutral species.
An integrated circuit of claim 9 wherein said electrically neutral species comprises Ar.
An integrated circuit comprising:
- a cap layer comprising silicon and carbon in contact with unannealed source/drain regions and a gate electrode of a transistor;
- wherein said cap layer contains an electrically neutral species.
Dependencies are inferred from the claim text.