Precise junction placement in vertical semiconductor devices using etch stop layers

A method of fabricating a vertical tunnel field effect transistor comprising;

• forming a first source/drain region having a majority composition of a first epitaxial semiconductor material and a first conductivity type, wherein a semiconductor etch stop layer of a second epitaxial semiconductor material is present within said first source/drain region between two layers of the first composition epitaxial semiconductor material;
• forming a material stack including at least a channel semiconductor material atop the first source/drain region of the device;
• etching the material stack to provide a channel region selectively to the semiconductor etch stop layer;
• and
• forming a second source/drain region having a second conductivity type positioned on the channel region.

A method of forming a semiconductor device comprising:

• forming a first portion of a first source/drain region comprised of a first layer of first semiconductor material having a first conductivity type;
• forming an etch stop layer of a second semiconductor material present of the first layer of epitaxial semiconductor material;
• forming a second layer of the first semiconductor material having the first conductivity type present on the etch stop layer to provide a second portion of the first source/drain region;
• forming a channel semiconductor material is present atop the first source/drain region;
• and
• forming a second source/drain region present atop the channel semiconductor material.