US 2017/0365679 A1 · SEMICONDUCTOR DEVICE HAVING A METAL GATE ELECTRODE STACK

Abstract

A semiconductor device includes a substrate and a gate dielectric layer on the substrate. The gate dielectric layer includes a single metal oxide layer. The semiconductor device includes a gate electrode stack on the gate dielectric layer. The gate electrode stack includes a metal filling line. The gate electrode stack includes a work function layer covering the sidewall and the bottom surface of the metal filling line. The gate electrode stack includes a capping layer in contact with the gate dielectric layer between sidewalls of the gate dielectric layer and sidewalls of the work function layer. The capping layer includes TaC and at least one of TiN or TaN. The gate electrode stack includes a barrier layer interposed between the capping layer and the sidewalls of the work function layer. The barrier layer comprises TaC and WN, and the barrier layer is in contact with the capping layer.

Claims20

Dependent claims

A semiconductor device, comprising:

a substrate;
a gate dielectric layer on the substrate, wherein the gate dielectric layer comprises a single metal oxide layer;
a gate electrode stack on the gate dielectric layer, the gate electrode stack including:
a metal filling line;
a work function layer covering the sidewall and the bottom surface of the metal filling line;
a capping layer in contact with the gate dielectric layer between sidewalls of the gate dielectric layer and sidewalls of the work function layer, wherein the capping layer comprises TaC and at least one of TiN or TaN;
a barrier layer interposed between the capping layer and the sidewalls of the work function layer, wherein the barrier layer comprises TaC and WN, and the barrier layer is in contact with the capping layer.

4 more elements

A method of making a semiconductor device, the method comprising:

forming a first dummy gate structure over a substrate, wherein the first dummy gate structure comprises a first dummy electrode;
forming a second dummy gate structure over the substrate, wherein the second dummy gate structure comprises a second dummy electrode;
removing the first dummy electrode to define a first opening;
removing the second dummy electrode to define a second opening, wherein the removing of the second dummy electrode occurs simultaneously with the removing of the first dummy electrode;
depositing a continuous gate dielectric layer in the first opening and the second opening, wherein the continuous gate dielectric layer comprises a single metal oxide layer;
depositing a continuous capping layer on a bottom surface and sidewalls of the continuous gate dielectric layer, wherein the continuous capping layer comprises TaC and a first additional material;
depositing a continuous barrier layer on a bottom surface and sidewalls of the continuous capping layer, wherein the continuous barrier layer comprises TaC and a second additional material, and the second additional material is different from the first additional material;
depositing a first work function layer over a bottom surface and sidewalls of the continuous barrier layer in the first opening;
depositing a second work function layer over a bottom surface and sidewalls of the continuous barrier layer in the second opening;
and
depositing a continuous metal layer over each of the first work function layer and the second work function layer.

8 more elements

Dependencies are inferred from the claim text.

Semiconductor device having a metal gate electrode stack

Life of this patent

Semiconductor device having a metal gate electrode stack

Life of this patent

Abstract

Claims20