Vertical non-volatile memory device and method for fabricating the same

A vertical non-volatile memory device, comprising:

• a substrate;
• a lower insulating layer on the substrate;
• a plurality of vertical channel layers on the lower insulating layer, extending in a vertical direction with respect to a top surface of the substrate, and spaced apart from one another in a horizontal direction with respect to the top surface of the substrate;
• a plurality of gate electrodes on the lower insulating layer, stacked alternately with interlayer insulating layers in the vertical direction along a side wall of the vertical channel layers, and extending in a first direction along the horizontal direction;
• a plurality of separation regions extending in the first direction and spaced apart in a second direction intersecting the first direction, the separation regions separating the gate electrodes from one another in the second direction;
• a lower wiring pattern including first wiring lines extending under the separation regions in the first direction and connected to the substrate through the lower insulating layer;
• and
• a horizontal channel layer on the insulating wiring layer and the lower wiring pattern and electrically connecting the vertical channel layers to the lower wiring pattern.

A vertical non-volatile memory device, comprising:

• a substrate;
• a plurality of vertical channels;
• a vertical stack of gate electrodes and insulating layers;
• and
• a plurality of wiring patterns between the substrate and the vertical stack of gate electrodes and insulating layers, wherein the vertical channels are connected to the wiring patterns.