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US 2017/0365597 A1Published application
Vertical Nanowire Transistor for Input/Output Structure
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJean-Pierre Colinge, Ta-Pen Guo, Carlos H. Diaz
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Abstract
An electrostatic discharge (ESD) protection circuit includes an input terminal, a transistor, and an output terminal. The input terminal is configured to receive an input signal. The transistor includes a first source/drain region, a second source/drain region, and a drift region that has a resistance in series between the first and second source/drain regions and that is configured to attenuate an ESD voltage in the input signal. The output terminal is connected to the second source/drain region.
Claims20
A method comprising:
- receiving an input signal;
- and
- attenuating an electrostatic discharge (ESD) voltage in the input signal by a drift region of a transistor that has a resistance in series between source and drain regions of the transistor.
A method comprising:
- receiving an input signal to a first top end of a first nanowire, wherein the first nanowire is of a first conductivity type;
- directing the input signal through the first nanowire to a doped region of the first conductivity type, wherein the doped region is underlying and connected to a bottom end of the first nanowire;
- directing the input signal from the doped region to an output;
- and
- clamping the input signal to be in a range between an electrical ground voltage and a positive power supply voltage using a PN junction, wherein the PN junction is formed between the doped region and a well region in contact with the doped region.
2 more elements
A method comprising:
- receiving a signal to a first top end of a first nanowire, wherein the first nanowire is of a first conductivity type;
- outputting the signal to an output, wherein the signal is directed through a drift region of the first nanowire, a channel region of the first nanowire, and a doped region in a substrate;
- connecting an electrical ground to a first region selected from a well region and a gate, wherein the well region is in contact with the doped region, and is of a second conductivity type opposite to the first conductivity type, and the gate encircles the channel region;
- and
- connecting a positive power supply voltage to a second region selected from the well region and the gate.
2 more elements
Dependencies are inferred from the claim text.