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US 2017/0365539 A1Published application
Semiconductor Packages and Methods of Fabrication Thereof
AssigneeInfineon Technologies Dresden GmbH
InventorsDirk Meinhold, Frank Daeche, Thorsten Scharf
Life of this patent
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Abstract
In accordance with an embodiment of the present invention, a semiconductor device includes a semiconductor chip having a first side and an opposite second side, and a chip contact pad disposed on the first side of the semiconductor chip. A dielectric liner is disposed over the semiconductor chip. The dielectric liner includes a plurality of openings over the chip contact pad. A interconnect contacts the semiconductor chip through the plurality of openings at the chip contact pad.
Claims22
A semiconductor device comprising:
- a conductive substrate;
- a first semiconductor chip disposed over the conductive substrate, the first semiconductor chip having a first side and an opposite second side;
- a first chip contact pad disposed on the first side of the first semiconductor chip;
- a second chip contact pad disposed on the second side of the second semiconductor chip, the second chip contact pad facing the conductive substrate;
- a dielectric liner disposed over the first semiconductor chip, the dielectric liner comprising a plurality of first openings over the first chip contact pad;
- an encapsulant disposed around the first semiconductor chip;
- and
- a first interconnect contacting the first semiconductor chip through the plurality of first openings at the first chip contact pad, the first interconnect disposed in the encapsulant.
5 more elements
A semiconductor device comprising:
- a conductive substrate;
- a first semiconductor chip having a first side and an opposite second side, the first semiconductor chip having a first chip contact pad on the first side and the second side being disposed over the conductive substrate;
- a first chip contact pad disposed in a dielectric layer of an uppermost metal level of the first semiconductor chip, the first chip contact pad comprising a plurality of metallic segments that are electrically interconnected and disposed in the dielectric layer, and wherein the plurality of metallic segments is separated by a plurality of first openings in the first chip contact pad;
- an encapsulant disposed over the first semiconductor chip;
- and
- an interconnect disposed through the encapsulant and the openings of the first chip contact pad.
3 more elements
A semiconductor device comprising:
- a first semiconductor chip having a first side and an opposite second side, the first semiconductor chip having a first chip contact pad on the first side;
- a first chip contact pad disposed on the first side, the first chip contact pad comprising a plurality of recesses;
- a dielectric liner disposed over the first semiconductor chip, the dielectric liner contacting the first semiconductor chip, the dielectric liner comprising a plurality of segments alternating with a plurality of openings;
- an encapsulant disposed over the first semiconductor chip;
- an opening in the encapsulant and extending to the plurality of recesses;
- and
- a conductive material disposed in the opening in the encapsulant and the plurality of openings in the dielectric liner.
4 more elements
A semiconductor device comprising:
- a conductive substrate;
- a first semiconductor chip having a first side and an opposite second side, the first semiconductor chip having a first chip contact pad on the first side and the second side facing the conductive substrate;
- a first chip contact pad disposed within a dielectric layer of an uppermost metal level of the first semiconductor chip, the first chip contact pad comprising a plurality of metallic segments that are electrically interconnected and disposed within the dielectric layer, and wherein the plurality of metallic segments is separated by openings in the first chip contact pad, wherein the plurality of metallic segments comprise a metallic top surface and sidewalls covered with an insulating sidewall spacer;
- an encapsulant over the first semiconductor chip;
- an opening in the encapsulant to expose the metallic top surface and the insulating sidewall spacer;
- and
- a conductive material disposed in the opening in the encapsulant and the openings of the first chip contact pad, wherein the conductive material covers the metallic top surface and the insulating sidewall spacer.
4 more elements
Dependencies are inferred from the claim text.