Semiconductor device

A semiconductor device, comprising:

• a fin region protruded from a substrate;
• a first field insulation layer on the substrate and extending in a first direction;
• a second field insulation layer on the substrate and extending in a second direction perpendicular to the first direction;
• a first gate on the fin region and extending in the first direction;
• a second gate on the first field insulation layer, a top surface of the first field insulation layer receiving only the second gate and no other gate;
• and
• a source/drain region adjacent to the first gate,
• wherein the top surface of the first field insulation layer is substantially coplanar with a top surface of the second field insulation layer.

A semiconductor device, comprising:

• a fin region protruded from a substrate;
• a first field insulation layer on the substrate and extending in a first direction;
• a second field insulation layer on the substrate and extending in a second direction perpendicular to the first direction;
• a first gate on the fin region and the second field insulation layer and extending in the first direction;
• a second gate on the first field insulation layer;
• and
• a pair of source/drain regions immediately adjacent to the second gate,
• wherein a bottom surface of the first gate on the second field insulation layer is substantially coplanar with a top surface of the first field insulation layer.

A semiconductor device, comprising:

• a fin region protruded from a substrate;
• a first field insulation layer on the substrate and extending in a first direction;
• a second field insulation layer on the substrate and extending in a second direction perpendicular to the first direction;
• a first gate on the fin region and the second field insulation layer and extending in the first direction;
• a second gate on the first field insulation layer, a top surface of the first field insulation layer receiving only the second gate and no other gate;
• and
• a source/drain region adjacent to the first gate,
• wherein the first gate includes a first gate electrode and a first gate insulating layer, and
• wherein a bottom surface of the first gate electrode on the second field insulation layer is upper than the top surface of the first field insulation layer.