Method of manufacturing high resistivity soi wafers with charge trapping layers based on terminated si deposition

A single crystal semiconductor handle structure comprising:

• a single crystal semiconductor handle wafer comprising two major, generally parallel surfaces, one of which is a front surface of the single crystal semiconductor handle wafer and the other of which is a back surface of the single crystal semiconductor handle wafer, a circumferential edge joining the front and back surfaces of the single crystal semiconductor handle wafer, a bulk single crystal semiconductor region, and the central plane of the single crystal semiconductor handle wafer between the front and back surfaces of the single crystal semiconductor handle wafer, wherein the single crystal semiconductor handle wafer has a minimum bulk resistivity of at least 100 Ohm-cm;
• a first semiconductor layer comprising a polycrystalline or an amorphous structure, wherein the first semiconductor layer comprises a material selected from the group consisting of silicon, SiGe, SiC, and Ge;
• a first passivating layer comprising a material selected from the group consisting of silicon dioxide, silicon nitride, and silicon oxynitride;
• and
• a second semiconductor layer comprising a polycrystalline or an amorphous structure, wherein the second semiconductor layer comprises a material selected from the group consisting of silicon, SiGe, SiC, and Ge.