Boosting channels of memory cells
AssigneeMicron Technology, Inc.
InventorsViolante Moschiano, Akira Goda, Mason A. Jones
Life of this patent
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Abstract
A method for programming a non-volatile memory device includes concurrently boosting channels of memory cells in a selected memory string and an unselected memory string of the memory device, discharging the boosted channels of the memory cells in the selected memory string, and programming a selected memory cell in the selected memory string after discharging the boosted channels in the selected memory string.
Claims21
A method of programming memory cells of a non-volatile NAND architecture memory array, comprising:
- applying a first bias voltage to a control gate of select transistors in selected and unselected NAND architecture memory strings, wherein the first bias voltage maintains the select transistors in an off state;
- applying a pass voltage to access lines of memory cells in the selected and unselected memory strings while the select transistors are in the off state to boost channels of the memory cells in the selected and unselected memory strings;
- discharging the boosted channels of the memory cells in the selected memory strings;
- and
- programming selected memory cells in the selected memory strings after discharging the boosted channels in the selected memory strings.
A method of operating a NAND architecture memory device, comprising:
- biasing select gate drain (SGD) transistors in selected and unselected NAND architecture memory strings to maintain the SGD transistors in an off state;
- biasing access lines of memory cells in the selected and unselected memory strings while the SGD transistors are in the off state to boost channels of the memory cells in the selected and unselected memory strings;
- biasing the SGD transistors in the selected memory strings to enter an on state to drive the boosted channels in the selected memory strings to ground while maintaining the boosted channels in the unselected memory strings;
- and
- programming selected memory cells in the selected memory strings after driving the boosted channels in the selected memory strings to ground.
A memory device, comprising:
- a memory array having a plurality of memory blocks;
- and
- a controller, wherein the controller is adapted to program memory cells in a selected memory block of the memory array by:
- concurrently boosting channels in selected memory strings and unselected memory strings of the selected memory block;
- driving the boosted channels in the selected memory strings to a reference potential while maintaining the boosted channels in the unselected memory strings;
- and
- programming selected memory cells in the selected memory strings after driving the boosted channels in the selected memory strings to the reference potential.
A three-dimensional NAND architecture memory device, comprising:
- a three-dimensional memory array having a plurality of memory blocks;
- and
- a controller, wherein the controller is adapted to program memory cells in a selected memory block of the three-dimensional memory array by:
- biasing select transistors in selected and unselected NAND architecture memory strings to maintain the select transistors in an off state;
- biasing access lines of memory cells in the selected and unselected memory strings while the select transistors are in the off state to boost channels of the memory cells in the selected and unselected memory strings;
- biasing the select transistors in the selected memory strings to enter an on state to drive the boosted channels in the selected memory strings to a reference potential while maintaining the boosted channels in the unselected memory strings;
- and
- programming selected memory cells in the selected memory strings after driving the boosted channels in the selected memory strings to the reference potential.
Dependencies are inferred from the claim text.