Synchronous dynamic random access memory (sdram) device, memory controller for same, and method of operating same
AssigneeSamsung Electronics Co., Ltd.
InventorsSeung-Jun SHIN, Tae-Young OH
Life of this patent
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Abstract
A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.
Claims21
-18. (canceled)
A synchronous dynamic random access memory (SDRAM) device comprising:
- a memory cell array;
- and
- a control logic configured to
- receive an active command during 2*N clock cycles, the N being an integer and 2*N clock cycles indicating doubled N clock cycles, the active command being composed of first portion and second portion, the first portion and the second portion being received consecutively in a first mode, and being received separately in a second mode;
- receive a CAS command during N clock cycles, the CAS command being received between the first portion and the second portion of the active command in the second mode;
- wherein a CAS command to CAS command delay (tCCD) is 3*N clock cycles in the first mode and the tCCD is 2*N clock cycles in the second mode respectively, the tCCD is a minimally required delay between two successive CAS commands.
A memory controller controlling a synchronous memory device, the memory controller configured to:
- transmit an active command during 2*N clock cycles, the N being an integer and 2*N clock cycles indicating doubled N clock cycles, the active command being composed of first portion and second portion, the first portion and the second portion being transmitted consecutively in a first mode and being transmitted separately in a second mode;
- and
- transmit a CAS command during N clock cycles, the CAS command being transmitted between the first portion and the second portion of the active command in the second mode,
- wherein a CAS command to CAS command delay (tCCD) is 3*N clock cycles in the first mode and the tCCD is 2*N clock cycles in the second mode respectively, the tCCD is a minimally required delay between two successive CAS commands.
A method of operating a synchronous dynamic random access memory (DRAM) device, the method comprising:
- receiving a first active command for a first access operation;
- receiving a second active command for a second access operation, the second active command being split into a first portion and a second portion, and each of the first portion and the second portion being received during N clock cycles respectively, the N being an integer;
- receiving a first read command for the first access operation during N clock cycles, the first read command being received between the first portion and the second portion of the second active command;
- receiving a second read command for the second access operation after receiving the second portion of the second active command;
- and
- outputting a first data as a result of the first access operation, a data transfer time of the first data being 2*N clock cycles, 2*N clock cycles indicating double of N clock cycles,
- wherein a minimally required time delay between the first read command and the second read command is sum of a first time duration required to receive the first read command and a second time duration required to receive the second portion of the second active command which is 2*N clock cycles.
Dependencies are inferred from the claim text.