Shift register unit and driving method, gate drive circuit, and display apparatus
AssigneeBoe Technology Group Co., Ltd.
InventorsHyunsic CHOI, Seungwoo Han
Life of this patent
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Abstract
The present application discloses an N-th shift register unit circuit including at least a gate-drive signal output sub-circuit, a pull-up control sub-circuit, and a pull-down control sub-circuit respectively connected between a pull-up node and a pull-down node and provided with a p-th clock signal in addition to an n-th clock signal. A driving method includes controlling the pull-down node at turn-off voltage level when the p-th clock signal is at turn-on voltage level during which the n-th clock signal is correspondingly rising to turn-on voltage level from turn-off voltage level.
Claims20
A method of driving a shift register unit, wherein the shift register unit is an N-th unit cascaded in the multi-stage gate driving circuit, wherein N is a positive integer, the N-th unit comprising:
- an N-th gate-drive signal output port;
- a gate-drive output sub-circuit including a capacitor connected between a pull-up node and the N-th gate-drive signal output port, and configured to output an n-th clock signal at the N-th gate drive signal output port, wherein n to be a remainder of N divided by 4 or n=4 if N is divisible by 4;
- a pull-up control sub-circuit connected to an (N−1)th gate-drive signal output port of a previous adjacent (N−1)th unit, a pull-down node, the pull-up node, and a fixed voltage port set to turn-off voltage level, and controlled by a m-th clock signal, wherein m is a remainder of (n+2) divided by 4 or equal to 4 if (n+2) is divisible by 4;
- and
- a pull-down control sub-circuit connected to the pull-up node, the fixed voltage port set to tum-off voltage level, the (N−1)th gate-drive signal output port, and the pull-down node, and controlled by the n-th clock signal and a p-th clock signal, wherein p is a remainder of (n+3) divided by 4 or equal to 4 if (n+3) is divisible by 4;
- the method comprising:
- controlling the p-th dock signal at turn-on voltage level during a time period corresponding to a rising, edge of the n-th clock signal during which the n-th clock signal changes from turn-off voltage level to turn-on voltage level;
- controlling the pull-down node to be set urn-on voltage level when the p-th clock signal is at turn-on voltage level;
- and
- resetting potential level of the N-th gate-drive signal output port to turn-off voltage level.
A shift register unit cascaded in a multi-stage gate driving circuit, wherein the shift register unit is N-th unit cascaded in the multi-stage gate driving circuit, wherein N is a positive integer, the N-th unit comprising:
- an N-th gate-drive signal output port;
- a gate-drive output sub-circuit including a capacitor connected between a pull-up node and the N-th gate-drive signal output port, and configured to control outputting of an n-th clock signal at the N-th gate drive signal output port when the pull-up node is at high voltage level, and to set low voltage level at the N-th gate-drive signal output port when a pull-down node is at high voltage level or an (N+3)-th carry signal output port of a (N+3)-th unit outputs a high voltage level signal, n being a remainder of N divided by 4 or equal to 4 if N is divisible by 4;
- a carry signal output sub-circuit configured to control outputting of the n-th clock signal at the N-th carry signal output port when the pull-up node is at high voltage level and to control outputting of a low voltage level signal at an N-th carry signal output port when the pull-down node is at high voltage level;
- a pull-up control sub-circuit connected to an (N−1)th gate-drive signal output port of a previous adjacent (N−1)th unit, a pull-down node, the pull-up node, and a fixed voltage port set to turn-off voltage level, and configured to set the pull-up node to high voltage level when a high voltage level signal is outputted at the (N−1)-th gate-drive signal output port from a previous adjacent shift register unit, and to set the pull-up node to In voltage level when the pull-down node, a m-th clock signal, or the (N+3)-th carry signal output port is at high voltage level, m being a remainder of (n+2) divided by 4 or equal to 4 if (n+2) is divisible by 4;
- a pull-down control sub-circuit connected to the pull-up node, the fixed voltage port set to turn-off voltage level, the (N−1)th gate-drive signal output port, and the pull-down node, and configured to set the pull-down node to low voltage level when the pull-up node, the (N−1)-th gate-drive signal output port, or the n-th clock signal is set to high voltage level, and to set the pull-down node to high voltage level when a p-th clock signal is set to high voltage level, p being a remainder of (n+3) divided by 4 or equal to 4 if (n+3) is divisible by 4;
- and
- a clock signal generator configured to generate the n-th clock signal, the m-th clock signal, and the p-th clock signal;
- wherein the p-th clock signal is at high voltage level when the n-th clock signal is on a rising edge from low voltage level to high voltage level.
Dependencies are inferred from the claim text.