Instruction and logic for performing a dot-product operation

A processor comprising:

• a first source vector register to store a first plurality of packed single-precision floating point values;
• a second source vector register to store a second plurality of packed single-precision floating point values;
• instruction decode circuitry to decode instructions;
• and
• an execution circuit to execute the instructions, wherein, in response to the instruction, decode circuitry decoding a dot-product instruction, the execution circuit is to:
• multiply selected packed single-precision floating point values in the first plurality with selected packed single-precision floating point values in the second plurality to generate a plurality of temporary products,
• store the temporary products in a first temporary storage location,
• add a first pair of the temporary products to generate a first sum,
• store the first sum in a second temporary storage location,
• add a second pair of the temporary products to generate a second sum,
• store the second sum in a third temporary storage location, and
• add the first and second sums to generate a cumulative sum,
• a destination register into which the execution unit is to selectively write the cumulative sum.