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US 2017/0364407 A1Published application
Semiconductor storage device
AssigneeToshiba Memory Corporation
InventorsYoshiaki OSADA, Katsuhiko HOYA
Life of this patent
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Abstract
According to one embodiment, a memory system includes: a first memory cell area where a first memory cell is provided; a second memory cell area where a second memory cell is provided; an ECC circuit which corrects an error of data stored by the first memory cell; and a control circuit which replaces the first memory cell with the second memory cell if the number of times an error is successfully corrected in the first memory cell reaches a first value.
Claims20
A memory system comprising:
- a first memory cell area where a first memory cell is provided;
- a second memory cell area where a second memory cell is provided;
- an ECC circuit which corrects an error of data stored by the first memory cell;
- and
- a control circuit which replaces the first memory cell with the second memory cell if a number of times an error is corrected in the first memory cell reaches a first value.
2 more elements
A memory system comprising:
- a first memory cell area where a first memory cell is provided;
- a second memory cell area where a second memory cell is provided;
- an ECC circuit which detects an error of data stored by the first memory cell;
- and
- a control circuit which replaces the first memory cell with the second memory cell if a number of times an error occurs in the first memory cell reaches a first value.
2 more elements
Dependencies are inferred from the claim text.