US 2017/0364358 A1 · OPERATION OF A MULTI-SLICE PROCESSOR IMPLEMENTING DEPENDENCY ACCUMULATION INSTRUCTION SEQUENCING

Abstract

Operation of a multi-slice processor that includes a plurality of execution slices. Operation of such a multi-slice processor includes: receiving a first instruction indicating a first target register; receiving a second instruction indicating the first target register as a source operand; responsive to the second instruction indicating the first target register as a source operand, updating a dependent count corresponding to the first instruction; and issuing, in dependence upon the dependent count for the first instruction being greater than a dependent count for another instruction, the first instruction to an execution slice of the plurality of execution slices.

Claims20

Dependent claims

A method of operation of a multi-slice processor, the multi-slice processor including a plurality of execution slices, wherein the method comprises:

receiving a first instruction indicating a first target register;
receiving a second instruction indicating the first target register as a source operand;
responsive to the second instruction indicating the first target register as a source operand, updating a dependent count corresponding to the first instruction;
and
issuing, in dependence upon the dependent count for the first instruction being greater than a dependent count for another instruction, the first instruction to an execution slice of the plurality of execution slices.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

15/186,744Filed 20 Jun 2016

Published

21 Dec 2017

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 9/3828
Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage: with global bypass, e.g. between…
G06F 9/3838
Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution: dependency mechanisms, e.g. register scoreboarding
G06F 9/3856
Instruction completion, e.g. retiring, committing or graduating: reordering of instructions, e.g. using queues or age tags
G06F 9/3858
Instruction completion, e.g. retiring, committing or graduating: result writeback, i.e. updating the architectural state or memory

Operation of a multi-slice processor implementing dependency accumulation instruction sequencing

Life of this patent

Operation of a multi-slice processor implementing dependency accumulation instruction sequencing

Life of this patent

Abstract

Claims20