Fetching Instructions in an Instruction Fetch Unit
AssigneeImagination Technologies Limited
InventorsAndrew David Webber, Daniel Ángel Chaver Martínez, Enrique Sedano Algarabel
Life of this patent
Estimating the term…
Loading patent…
AssigneeImagination Technologies Limited
InventorsAndrew David Webber, Daniel Ángel Chaver Martínez, Enrique Sedano Algarabel
Estimating the term…
A method in an instruction fetch unit configured to initiate a fetch of an instruction bundle from a first memory and to initiate a fetch of an instruction bundle from a second memory, wherein a fetch from the second memory takes a predetermined fixed plurality of processor cycles, the method comprising: identifying that an instruction bundle is to be selected for fetching from the second memory in a predetermined future processor cycle; and initiating a fetch of the identified instruction bundle from the second memory a number of processor cycles prior to the predetermined future processor cycle based upon the predetermined fixed plurality of processor cycles taken to fetch from the second memory
A method in an instruction fetch unit configured to initiate a fetch of an instruction bundle from a first memory and to initiate a fetch of an instruction bundle from a second memory, wherein a fetch from the second memory takes a predetermined fixed plurality of processor cycles, the method comprising:
An instruction fetch unit configured to initiate a fetch of an instruction bundle from a first memory and to initiate a fetch of an instruction bundle from a second memory, and wherein a fetch from the second memory takes a predetermined fixed number of processor cycles, the instruction fetch unit comprising:
A computer readable storage medium having stored thereon a computer readable description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an instruction fetch unit configured to initiate a fetch of an instruction bundle from a first memory and to initiate a fetch of an instruction bundle from a second memory, and wherein a fetch from the second memory takes a predetermined fixed plurality of processor cycles, wherein the instruction fetch unit comprises a control module configured to:
Dependencies are inferred from the claim text.