US 2017/0364305 A1Published application

Clock-skew-tolerant memory updating

AssigneeOracle International Corporation

InventorsJungyong Lee, Jinho Kwack, Tsunghsun Hsieh

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Abstract

Embodiments include systems and methods for providing robust clock-skew-tolerant memory updating in high-speed memory circuits. For example, in each memory update interval, update of a pre-memory with un-validated update data begins when a potential match is detected between a tag memory and a key (whether according to a base clock or a delayed clock); but the update data is not considered valid (nor is it written out as such) until a determination is made according to the delayed clock. The un-validated update data can be written out from the pre-memory as validated update data for the memory update interval upon detection of a data valid indication generated from the delayed hit indication.

Claims20

Dependent claims

A method for clock-skew-tolerant memory updating, the method comprising:

generating a hit indication in association with a memory update interval when a key signal matches a tag memory signal at a first clock signal trigger time in the memory update interval;
generating a delayed hit indication in association with the memory update interval when the key signal matches the tag memory signal at a first delayed clock signal trigger time in the memory update interval;
triggering updating of a pre-memory with un-validated data for the memory update interval in response to detecting either of the hit indication or the delayed hit indication;
triggering a data valid indication for the memory update interval in response to detecting at least the delayed hit indication;
and
reading out the un-validated data from the pre-memory as validated data for the memory update interval in response to detecting the data valid indication for the memory update interval at a second clock signal trigger time in the memory update interval.

3 more elements

A memory update structure comprising:

a data validation sub-structure having:
a clock signal input;
a delayed clock signal input that is a delayed version of the clock signal input;
a match signal input that is HIGH when a tag memory signal matches a key signal, and is LOW otherwise;
a write enable signal output;
and
a data valid signal output,
wherein, in a given memory update interval of the clock signal input:
the write enable signal output is triggered HIGH in response to the match signal being HIGH at a trigger time of either the clock signal input or the delayed clock signal input;
and
the data valid signal output is HIGH when the match signal is HIGH at the trigger time of at least the delayed clock signal input.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/184,776Filed 16 Jun 2016
Published: 21 Dec 2017
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 12/00
Accessing, addressing or allocating within memory systems or architectures
G06F 13/00
Interconnection of, or transfer of information or other signals between, memories, input/output
G06F 13/4243
Being a memory bus: with synchronous protocol
G06F 12/0895
Caches characterised by their organisation or structure: of parts of caches, e.g. directory or tag array

Family

US 9,928,007 B2Related patent
US 2017/0364305 A1This patent

From the US filing history. Foreign family members aren’t listed.

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