Memory devices having distributed controller systems

An apparatus, comprising:

• a memory array;
• an analog voltage generation circuit in communication with the memory array;
• an analog controller configured to determine at least one analog voltage for performing a particular access operation on the memory array, and configured to generate control signals to the analog voltage generation circuit to generate the determined at least one analog voltage for the particular access operation;
• a data cache in communication with the memory array;
• a data cache controller configured to determine whether the data cache is to be configured to accept data from the memory array or to provide data to the memory array to perform the particular access operation, and configured to generate control signals to the data cache to configure the data cache to the determined configuration;
• and
• a master controller in communication with the memory array, the analog controller, and the data cache controller;
• wherein the master controller is configured to generate an indication in response to an interpreted command to perform the particular access operation.

An apparatus, comprising:

• a memory array;
• an analog voltage generation circuit in communication with the memory array;
• an analog controller in communication with the analog voltage generation circuit;
• a data cache in communication with the memory array;
• a data cache controller in communication with the data cache;
• and
• a master controller in communication with the memory array, the analog controller, and the data cache controller;
• wherein the master controller is configured to generate a first indication in response to an interpreted command of a first type indicative of a desire to perform a first access operation on the memory array, and to generate a second indication in response to an interpreted command of a second type indicative of a desire to perform a second access operation on the memory array;
• wherein the analog controller is configured to:
• determine, in response to the first indication, at least one analog voltage to be generated by the analog voltage generation circuit for the apparatus to perform the first access operation;
• and
• determine, in response to the second indication, at least one analog voltage to be generated by the analog voltage generation circuit for the apparatus to perform the second access operation;
• wherein the data cache controller is configured to:
• determine, in response to the first indication, that the data cache should be configured to accept data from the memory array;
• and
• determine, in response to the second indication, that the data cache should be configured to provide data to the memory array.